The subject matter of the present invention relates generally to circuitry for converting CMOS logic levels to corresponding ECL logic levels to permit the coupling of CMOS circuits to ECL circuits and to logic circuit buffer drivers, of the type that are used in networks where matched impedance terminated transmission line communication is required.
To couple a CMOS circuit to an ECL circuit, the difference between the output voltages from the one circuit and the input voltages needed by the second circuit must be generated by some form of interfacing circuit. A CMOS circuits' logic level "1" will approach the power supply value which is generally three to five volts, while its logic level "0" will be near the reference or ground level. On the other hand, an ECL circuits' logic level "1" will approach -0.8 volts while its logic level "0" will approach -1.68 volts.
Circuitry for performing an interface function should contain only a few transistors in order to minimize the use of silicon area and to minimize propagation delays through the transistors. The interfacing circuitry additionally should maintain a relatively constant low output impedance during the transition.
A patent of interest is U.S. Pat. No. 4,453,095, entitled "ECL MOS Buffer Circuits" by R.S. Wrathall. The circuit described in that patent is an input buffer for receiving on its input ECL logic signals and for providing at its output CMOS signals.
Another patent of interest is U.S. Pat. No. 4,538,076, entitled "Level Converter Circuit", by H. Shimada. The circuit of that patent is a level converter for converting a first logic signal, using a lower voltage supply as a base potential, into a second logic signal having a higher voltage supply as a base potential.
Another patent of interest is U.S. Pat. No. 4,563,595, entitled "CMOS Schmitt Trigger Circuit for TTL Logic Levels", by B.K. Bose. The circuit of that patent is a TTL to CMOS translator using the hysteresis normally found in Schmitt triggers.
Another patent of interest is U.S. Pat. No. 4,563,601, entitled "Level Conversion Input Circuit", by N.A. Kokubunji et al. The circuit of that patent converts an ECL level to a CMOS level. The circuit is adapted to provide a level conversion input circuit which has high speed performance and low power consumption while being relatively stable as to the fluctuation of temperature and power source voltages.